The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a micro-trench storage capacitor.
Recently, requirement for improvement in a high density integration of large scale integrated circuits has been on the increase thereby a minimization in size of each element constituting the large scale integrated circuits is also required. The large scale integrated circuits generally includes dynamic random access memories involving may capacitors. To obtain a further improvement in a high density integration of the large scale integrated circuit, a further minimization in size of the storage capacitors constituting memory devices is required.
On the other hand, the storage capacitor is of course required to have a necessary capacity. As well known, the capacity of the capacitor depends upon a contact area between electrode and dielectric film constituting the capacitor. A large contact area between the electrode and the dielectric film provides the capacitor with a large capacity.
To realize a further improvement in a high density in integration of the large scale integrated circuits involving the storage capacitors, each of the storage capacitor is required to have a possible small occupied area and a possible large contact surface between electrode and dielectric film involved in the capacitor. For that purpose, various structures of the capacitor has been proposed.
One of conventional structures of the capacitors is disclosed in the Japanese laid-open patent application No. 4-196435 in which a hemispheric grain polysilicon is used as a bottom electrode to allow the capacitor to have a large storage capacitor in a limited small occupied area.
Another of the conventional structures of the capacitors is disclosed in 1992 December, Proceeding of the 43rd Symposium on Semiconductors and Integrated Circuits Technology, pp. 126-131 in which a micro-trench storage capacitor was proposed. Fabrication processes of this conventional capacitor will be described in detail with reference to FIGS. 1A to 1C.
With reference to FIG. 1A, an isolation silicon oxide film 20 is formed on a surface of a silicon substrate 1. A silicon nitride film is deposited on a surface of the isolation oxide film 20 by use of a chemical vapor deposition method. A silicon oxide film 22 is further deposited on a surface of the silicon nitride film 21 by use of a chemical vapor deposition method. A contact hole is formed by use of both lithography and etching to penetrate through the triplet films or the silicon oxide film 22, the silicon nitride film 21 and the isolation silicon oxide film 20 until a part of the surface of the silicon substrate 1 is exposed through the contact hole. A chemical vapor deposition is subsequently carried out to deposit a polysilicon film 23 having a thickness of 400 nanometers on a top surface of the silicon oxide film 22 thereby the contact hole is filed with the polysilicon. The polysilicon film 23 is subjected to an introduction of phosphorus by use of diffusion. A silicon oxide film 24 having a thickness of 20 nanometers is deposited on a top surface of the phosphorus-doped polysilicon by use of a chemical vapor deposition. The polysilicon film 23 and the silicon oxide film 24 are then defined by lithography and etching processes thereby the remaining part of the polysilicon film serves as a bottom electrode 23. Hemispherical grains 25 of silicon are formed by use of a chemical vapor deposition method and subsequent annealing process if any on a top surface of the silicon oxide film 24, exposed side walls of the polysilicon film 23 and the top surface of the oxide silicon film 22.
With reference to FIG. 1B, the silicon oxide film 24 is subjected to a dry etching using the hemispherical grains 25 as masks so that the silicon oxide film 24 partially remains only under the hemispherical grains 25.
With reference to FIG. 1C, the polysilicon film 23 serving as the bottom electrode is subjected to a dry etching using the remaining silicon oxide film 24 as a mask to form trench grooves 5 under apertures of the remaining silicon oxide film 24 so that the bottom electrode has alternate trench grooves and trench pillars.
Although illustration is omitted, the silicon oxide films 24 and 22 are etched by use of fluorate. A dielectric film is formed along a surface of the bottom electrode with the trench grooves and the trench pillars. A polysilicon film is deposited on the dielectric film for an introduction of phosphorus and subsequent lithography and etching processes to define a top electrode of the polysilicon film. This results in a completion of the formation of the micro-trench storage capacitor.
The micro-trench structure comprising the alternate trench pillars and trench grooves enlarges the contact surface between the dielectric film and either of the top and bottom electrodes. Namely, the micro-trench structure comprising the alternate trench pillars and trench grooves allows the storage capacitor to have a sufficiently large capacity and a small occupied area for implemention in a high integration of the storage capacitors.
The above conventional fabrication methods for the micro-trench storage capacitors is, however, engaged with problems as the hemispherical grains were used as mask to form the micro-trench grooves. It is difficult to control the grain size which defines the size of the micro-trench pillars and apertures. To grow the grain, a clean surface of the silicon is also required, although it is difficult to keep the required clean surface of the silicon. It is further required to keep a clean atmosphere in a chamber involved in the heat treatment system, although it is difficult to keep the required clean atmosphere. Those result in a lowering of an efficiency in manufacturing of the storage capacitors.
Another conventional fabrication method for a storage capacitor is disclosed in the Japanese patent publication No. 1-119049 in which two imcompatible materials are applied on a substrate for removal of one of them and subsequent anisotropic etching process using the other one of the materials as a mask to form grooves in a bottom electrode involved in the storage capacitor.
This conventional fabrication method is also engaged with problems as described below. Since the two different materials are applied on the substrate, the resultant films prepared by application of the materials has a relatively large variation in the thickness. Particularly, when the thickness of the film is made so thin as to form an irregularity of not less than 100 nanometers, a variation in the thickness of the film is enlarged thereby resulting in a serious problem in fabricating the storage capacitor.
It is therefore required to develop a novel fabrication method for the required storage capacitor without the use of any growth of crystal grain or application of the material for the mask on the substrate.